In complementary metal oxide semiconductor (CMOS) integrated circuit design, the proximity of a transistor (e.g., a field effect transistor (FET)) to an edge of an implanted well affects its threshold voltage. This effect is known as the well proximity effect. The well proximity effect is due to some of the ions in the implantation process scattering from the edge of the photoresist mask and being implanted in the silicon surface near the mask edge. The well proximity effect is particularly inherent in deep sub-micron CMOS process technology. In general, the closer a transistor is to a well edge, the more the threshold voltage is affected. Furthermore, if more than one well edge is present, the well proximity effect is cumulative.
FIG. 1 shows an exemplary graph 100 generally illustrating the well proximity effect. The graph 100 includes an axis 102 representing the distance of the transistor from the edge of an implanted well, and an axis 104 representing a change in threshold voltage of the transistor. A curve 106 generally depicts the change in threshold voltage versus distance from the well edge. When the transistor is relatively far from the edge, there is little or no change in threshold voltage due to well proximity effect. As the transistor is moved closer to the well edge, the threshold voltage changes in a non-linear fashion. The shape of the curve 106 is dictated by, among other factors, the type of transistor (e.g., n-mos FET or p-mos FET) and the thickness of the gate oxide (e.g., thickox, midox, thinox, etc.).
The well proximity effect should be accounted for during analysis of a circuit design in order to generate functional designs. Accordingly, there exists a need in the art for a method and apparatus for modeling transistors in an integrated circuit design that accounts for the well proximity effect.